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13.15.8 Master Mode
The I²S is configured as a master device by
setting I2SCFG0.MASTER to 1. When the
module is in master mode, it drives the SCK
and WS lines.
13.15.8.1 Clock Generation
When the I²S is configured as master, the
frequency of the SCK clock signal must be set
to match the sample rate. The clock frequency
must be set before master mode is enabled.
SCK is generated by dividing the system clock
using a fractional clock divider. The amount of
division is given by the 15 bit numerator, NUM ,
and 9-bit denominator, DENOM, as shown in the
following formula:
F_sck =
F_clk
NUM
2(
)
DENOM
where ^NUM > 3.35
DENOM
F_clk is the system clock frequency and F_sck is the
I²S SCK sample clock frequency.
C2510Fx / CC2511Fx
The value of the numerator is set in the
I2SCLKF2.NUM[14:8]:I2SCLKF1.NUM[7:0]
registers and the denominator value is set in
I2SCLKF2.DENOM[8]:I2SCLKF0.DENOM[7:0].
Please note that to stay within the timing
requirements of the I²S specification [6], a
minimum value of 3.35 should be used for the
(NUM / DENOM) fraction.
The fractional divider is made such that most
normal sample rates should be supported for
most normal word sizes with a 24 MHz system
clock frequency (CC2511Fx). Examples of
supported configurations for a 24 MHz system
clock are given in Table 57. Table 58 shows the
configuration values for a 26 MHz system clock
frequency. Notice that the generated I²S
frequency is not exact for the 44.1 kHz, 16 bits
word size configuration at 26 MHz. The
numbers are calculated using the following
formulas, where F_s is the sample rate and W is
the word size:
F_s
=
F_sck
2 *W
CLKDIV = ^NUM = ^Fclk
DENOM 4 *W * F_s
F_sck (kHz)
8
8
44.1
48
Word Size (W)
8
16
16
16
CLKDIV
93.75
46.875
8.503401
7.8125
I2SCLKF2 I2SCLKF1 I2SCLKF0 Exact
0x01
0x77
0x04
Yes
0x01
0x77
0x08
Yes
0x04
0xE2
0x93
Yes
0x00
0x7D
0x10
Yes
Table 57: Example I²S Clock Configurations (CC2511Fx, 24 MHz)
F_sck (kHz)
8
8
Word Size (W)
8
16
CLKDIV
101.5625
50.78125
I2SCLKF2 I2SCLKF1 I2SCLKF0 Exact
0x06
0x59
0x10
Yes
0x06
0x59
0x20
Yes
44.1
16
48
16
9.21201
0x8A
0x2F
0x1B
No
8.46354
0x06
0x59
0xC0
Yes
Table 58: Example I²S Clock Configurations (CC2510Fx, 26 MHz)
13.15.8.2 Word Size
The word size must be set before master
mode is enabled. The word size is the number
of bits used for each sample and can be set to
a value between 1 and 33. To set the word
size, write word size – 1 to the
I2SCFG1.WORDS[4:0] bits. Setting the word
size to a value of 17 or more causes the I²S to
pad each word with 0’s in the least significant
bits since the data registers provide maximum
16 bits. This feature allows samples to be sent
SWRS055D
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