STE10 Datasheet, PDF (64/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 24. 10BASE-T Normal Link Pulse(NLP) Timings Specifications
Symbol
Parameter
Test Condition
Min. Typ. Max. Units
NLP Width
10Mbps
100
ns
NLP Period
10Mbps
8
24
ms
Figure 21. Normal Link Pulse timings
Tnpw
Tnpc
Table 25. Auto-Negotiation Fast Link Pulse(FLP) Timings Specifications
Symbol
Parameter
Test Condition
Min. Typ. Max. Units
Tflpw FLP Width
100
Clock pulse to clock pulse period
111 125 139
Clock pulse to Data pulse period
55.5 62.5 69.5
Number of pulses in one burst
17
33
Burst Width
2
FLP Burst period
8
16
24
Figure 22. Fast Link Pulse timing
Table 26. 100BASE-TX Transmitter AC Timings Specification
Symbol
Parameter
Test Condition
Tjit TDP-TDN Differential Output
Peak Jitter
64/66
Min.
Typ.
Max.
1.4
Units
ps