STE10 Datasheet, PDF (13/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val RW Type
15~8
DS
Driver Space for implementation-specific purpose. Since this
0
R/W
area won’t be cleared upon software reset, an STE10/100
driver can use this R/W area as user-specified storage.
7~0
---
reserved
CR32(offset = 80h), SIG - Signature of STE10/100
31~16
DID
Device ID, the device ID number of the STE10/100.
0981h
RO
15~0
VID
Vendor ID
1317h
RO
CR48(offset = c0h), PMR0, Power Management Register0.
31
PSD3c, PME_Support.
X1111b
RO
30
PSD3h, The STE10/100 will assert PME# signal while in the D0, D1,
29
PSD2, D2, D3hot and D3cold power state. The STE10/100 supports
28
PSD1, Wake-up from the above five states. Bit 31 (support wake-up
27
PSD0 from D3cold) is loaded from EEPROM after power-up or
hardware reset. To support the D3cold wake-up function, an
auxiliary power source will be sensed during reset by the
STE10/100 Vaux_detect pin. If sensed low, PSD3c will be set
to 0; if sensed high, and if D3CS (bit 31of CSR18) is set
(CSR18 bits 16~31 are recalled from EEPROM at reset), then
bit 31 will be set to 1.
26
D2S D2_Support. The STE10/100 supports the D2 Power
Management State.
1
RO
25
D1S D1_Support. The STE10/100 supports the D1 Power
Management State.
1
RO
24~22
AUXC Aux Current. These three bits report the maximum 3.3Vaux
XXXb
RO
current requirements for STE10/100 chip. If bit 31 of PMR0 is
‘1’, the default value is 111b, meaning the STE10/100 needs
375 mA to support remote wake-up in D3cold power state.
Otherwise, the default value is 000b, meaning the STE10/100
does not support remote wake-up from D3cold power state.
21
DSI
The Device Specific Initialization bit indicates whether any
0
RO
special initialization of this function is required before the
generic class device driver is able to use it.
0: indicates that the function does not require a device-specific
initialization sequence following transition to the D0
uninitialized state.
20
---
Reserved.
19
PMEC PME Clock. Indicates that the STE10/100 does not rely on the
0
RO
presence of the PCI clock for PME# operation
18~16
VER Version. The value of 010b indicates that the STE10/100
010b
RO
complies with Revision 1.0a of the PCI Power Management
Interface Specification.
15~8
NIP
Next Item Pointer. This value is always 0h, indicating that
there are no additional items in the Capabilities List.
00h
RO
7~0
CAPID Capability Identifier. This value is always 01h, indicating the
01h
RO
link list item as being the PCI Power Management Registers.
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