STE10 Datasheet, PDF (47/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

6.3.2 Transmit pre-fetch data flow
s Transmit FIFO size=2K-byte
s two packets in the FIFO at the same time
s meet the transmit min. back-to-back
Figure 10. Transmit data flow of pre-fetch data
STE10/100
place the 1st packet data into host memory
issue transmit demand
FIFO-to-host memory operation (1st packet)
Transmit enable
place the 2nd packet data into host memory
check point
FIFO-to-host memory operation (2nd packet)
place the 3rd packet data into host memory
check point
FIFO-to-host memory operation (3rd packet)
time
: handled by driver
transmit threshold
IFG
1st packet
check the next
packet
2nd packet
1st packet is
transmitted, check
the 3rd packet
: handled by STE10/100
6.3.3 Transmit early interrupt Scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
Host to TX-FIFO Memory
Operation
Transmit data from FIFO to Media
Normal Interrupt after Transmit
Completed
Driver return buffer to upper layer
Early Interrupt after Host to TX-
FIFO Operation Completed
Driver return buffer to upper layer
time
: handled by driver
The saved time when transmit
early interrupt is implemented
: handled by STE10/100
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