STE10 Datasheet, PDF (5/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
4.0 4. PIN DESCRIPTION
Table 1. Pin Description
Pin No. Name
Type
PCI bus Interface
113
INTA#
O/D
114
RST#
I
116 PCI-CLK
I
117
GNT#
I
118
REQ#
O
119
PME#
O
OD
120,121 AD-31,30
I/O
123,124 AD-29,28
126,127 AD-27,26
1,2 AD-25,24
6,7 AD-23,22
9,10 AD-21,20
12,13 AD-19,18
15,16 AD-17,16
29,30 AD-15,14
32~35 AD-13~10
37
AD-9
41
AD-8
43,44 AD-7, 6
46,47
AD-5,4
49,50
AD-3,2
52,53
AD-1,0
3
C-BEB3
I/O
17
C-BEB2
28
C-BEB1
42
C-BEB0
4
IDSEL
I
18
FRAME#
I/O
20
IRDY#
I/O
Description
PCI interrupt request. STE10/100 asserts this signal when one of the interrupt
event is set.
PCI Reset signal to initialize the STE10/100. The RST signal should be asserted
for at least 100µs to ensure that the STE10/100 completes initialization. During
the reset period, all the output pins of STE10/100 will be placed in a high-
impedance state and all the O/D pins are floated.
PCI clock input to STE10/100 for PCI Bus functions. The Bus signals are
synchronized relative to the rising edge of PCI-CLK PCI-CLK must operate at a
frequency in the range between 20MHz and 33MHz to ensure proper network
operation
PCI Bus Granted. This signal indicates that the STE10/100 has been granted
ownership of the PCI Bus as a result of a Bus Request.
PCI Bus Request. STE10/100 asserts this line when it needs access to the PCI
Bus.
The Power Management Event signal is an open drain, active low signal. The
STE10/100 will assert PME# to indicate that a power management event has
occurred.
When WOL (bit 18 of CSR18) is set, the STE10/100 is placed in Wake On LAN
mode. While in this mode, the STE10/100 will activate the PME# signal upon
receipt of a Magic Packet frame from the network.
In the Wake On LAN mode, when LWS (bit 17 of CSR18) is set, the LAN-WAKE
signal follows HP’s protocol; otherwise, it is IBM protocol.
Multiplexed PCI Bus address/data pins
Bus command and byte enable
Initialization Device Select. This signal is asserted when the host issues
configuration cycles to the STE10/100.
Asserted by PCI Bus master during bus tenure
Master device is ready to begin data transaction
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