STE10 Datasheet, PDF (62/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 22. Flash Interface Timings
Symbol
Parameter
Tfcyc Read/Write Cycle Time
Tfce Address to Read Data Setup
Time
Tfce CS# to Read Data Setup Time
Tfoe OE# Active to Read Data Setup
Time
Tfdf OE# Inactive to Data Driven
Delay Time
Tfas Address Setup Time before WE#
Tfah Address Hold Time after WE#
Tfcs CS# Setup Time before WE#
Tfch Address Hold Time after WE#
Tfds Data Setup Time
Tfdh Data Hold Time
Tfwpw Write Pulse Width
Tfwph Write Pulse Width High
Tfasc Address Setup Time before CS#
Tfahc Address Hold Time after CS#
Figure 18. Flash write timings
Test Condition
Tfcyc
ADDRESS
Tfasc
Tfasw
Tfah
Tahw
Min.
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS#
WE#
DATA
Tfcss
Tfwph
Tfwpw
Tfcsh
Tfds
Tfdh
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