STE10 Datasheet, PDF (30/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
7~0
PAB0 physical address byte 0
From
R/W
EEPROM
CSR26(offset = a8h) - PAR1, physical address register 1, automatically recalled from EEPROM
31~24
---
reserved
23~16
---
reserved
15~8
PAB5 physical address byte 5
From
R/W
EEPROM
7~0
PAB4 physical address byte 4
From
R/W
EEPROM
For example, physical address = 00-00-e8-11-22-33
PAR0= 11 e8 00 00
PAR1= XX XX 33 22
PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000).
CSR27(offset = ach) - MAR0, multicast address register 0
31~24
MAB3 multicast address byte 3 (hash table 31:24)
00h
R/W
23~16
MAB2 multicast address byte 2 (hash table 23:16)
00h
R/W
15~8
MAB1 multicast address byte 1 (hash table 15:8)
00h
R/W
7~0
MAB0 multicast address byte 0 (hash table 7:0)
00h
R/W
CSR28(offset = b0h) - MAR1, multicast address register 1
31~24
MAB7 multicast address byte 7 (hash table 63:56)
00h
R/W
23~16
MAB6 multicast address byte 6 (hash table 55:48)
00h
R/W
15~8
MAB5 multicast address byte 5 (hash table 47:40)
00h
R/W
7~0
MAB4 multicast address byte 4 (hash table 39:32)
00h
R/W
MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000).
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