STE10 Datasheet, PDF (37/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 8. Transceiver registers Descriptions
Bit #
Name
Descriptions
Default Val RW Type
5
ISOTX Transmit Isolation. When 1, isolate from MII and tx+/-. This bit
0
R/W
must be 0 for normal operation
4~2
CMODE Reports current transceiver operating mode.
000: in auto-negotiation
001: 10Base-T half duplex
010: 100Base-TX half duplex
011: reserved
100: reserved
101: 10Base-T full duplex
110: 100Base-TX full duplex
111: isolation, auto-negotiation disable
000
RO
1
DISMLT Disable MLT3.
0: the MLT3 encoder and decoder are enabled.
1: the MLT3 encoder and decoder are bypassed.
0
R/W
0
DISCRM Disable Scramble.
0: the scrambler and de-scrambler is enabled.
1: the scrambler and de-scrambler are disabled.
0
R/W
5.4 Descriptors and Buffer Management
The STE10/100 provides receive and transmit descriptors for packet buffering and management.
5.4.1 Receive descriptor
Table 9. Receive Descriptor Table
31
RDES0 Own
Status
RDES1
---
Control
Buffer2 byte-count
RDSE2
Buffer1 address (DW boundary)
RDSE3
Buffer2 address (DW boundary
Note: 1. Descriptors and receive buffers addresses must be longword aligned
0
Buffer1 byte-count
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