STE10 Datasheet, PDF (20/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
15~14
TR
transmit threshold control
00: 128-bytes (100Mbps), 72-bytes (10Mbps)
01: 256-bytes (100Mbps), 96-bytes (10Mbps)
10: 512-bytes (100Mbps), 128-bytes (10Mbps)
11: 1024-bytes (100Mbps), 160-bytes (10Mbps)
00
R/W*
13
ST
Stop transmit
0: stop (default)
1: start
0
R/W
12
FC
Force collision mode
0
R/W**
0: disable
1: generate collision upon transmit (for testing in loop-back
mode)
11, 10
OM
Operating Mode
00
00: normal
01: MAC loop-back, regardless of contents of XLBEN (bit 14 of
XR0, XCVR loop-back)
10,11: reserved
R/W**
9, 8
---
reserved
7
MM
Multicast Mode
1: receive all multicast packets
0
R/W***
6
PR
Promiscuous Mode
1: receive any good packet.
0: receive only the right destination address packets
1
R/W***
5
SBC Stop Back-off Counter
0
R/W**
1: back-off counter stops when carrier is active, and resumes
when carrier is dropped.
0: back-off counter is not effected by carrier
4
---
reserved
3
PB
Pass Bad packet
0
R/W***
1: receives any packets passing address filter, including runt
packets, CRC error, truncated packets. For receiving all
bad packets, PR (bit 6 of CSR6) should be set to 1.
0: filters all bad packets
2
---
reserved
1
SR
Start/Stop Receive
0
R/W
0: receive processor will enter stop state after the current
frame reception is completed. This value is effective only
when the receive processor is in the running or suspending
state. Note: In “Stop Receive” state, the PAUSE packet and
Remote Wake Up packet will not be affected and can be
received if the corresponding function is enabled.
1: receive processor will enter running state.
0
---
reserved
W* = only write when the transmit processor stopped.
W** = only write when the transmit and receive processor both stopped.
W*** = only write when the receive processor stopped.
CSR7(offset = 38h), IER - Interrupt Enable Register
20/66