STE10 Datasheet, PDF (21/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
31~17
---
reserved
16
NIE
Normal Interrupt Enable
0
R/W
1: enables all the normal interrupt bits (see bit 16 of CSR5)
15
AIE
Abnormal Interrupt Enable
0
R/W
1: enables all the abnormal interrupt bits (see bit 15 of CSR5)
14
---
reserved
13
FBEIE Fatal Bus Error Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the fatal bus error interrupt
12
---
Reserved
11
GPTIE General Purpose Timer Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the general purpose timer expired interrupt.
10
---
Reserved
9
RWTIE Receive Watchdog Time-out Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the receive watchdog time-out interrupt.
8
RSIE Receive Stopped Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the receive stopped interrupt.
7
RUIE Receive Descriptor Unavailable Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the receive descriptor unavailable interrupt.
6
RCIE Receive Completed Interrupt Enable
0
R/W
1: this bit in conjunction with NIE (bit 16 of CSR7) will enable
the receive completed interrupt.
5
TUIE Transmit Under-flow Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the transmit under-flow interrupt.
4
---
Reserved
3
TJTTIE Transmit Jabber Timer Time-out Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the transmit jabber timer time-out interrupt.
2
TDUIE Transmit Descriptor Unavailable Interrupt Enable
0
R/W
1: this bit in conjunction with NIE (bit 16 of CSR7) will enable
the transmit descriptor unavailable interrupt.
1
TPSIE Transmit Processor Stopped Interrupt Enable
0
R/W
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the transmit processor stopped interrupt.
0
TCIE Transmit Completed Interrupt Enable
0
R/W
1: this bit in conjunction with NIE (bit 16 of CSR7) will enable
the transmit completed interrupt.
CSR8(offset = 40h), LPC - Lost packet counter
21/66