STE10 Datasheet, PDF (1/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
PCI 10/100 ETHERNET CONTROLLER
WITH INTEGRATED PHY (5V)
PRODUCT PREVIEW
1.0 DESCRIPTION
The STE10/100 is a high performance PCI Fast Eth-
ernet controller with integrated physical layer inter-
face for 10BASE-T and 100BASE-TX application.
It was designed with advanced CMOS technology to
provide glueless 32-bit bus master interface for PCI
bus, boot ROM interface, CSMA/CD protocol for Fast
Ethernet, as well as the physical media interface for
100BASE-TX of IEEE802.3u and 10BASE-T of
IEEE802.3. The auto-negotiation function is also
supported for speed and duplex detection.
The STE10/100 provides both half-duplex and full-
duplex operation, as well as support for full-duplex
flow control. It provides long FIFO buffers for trans-
mission and receiving, and early interrupt mecha-
nism to enhance performance. The STE10/100 also
supports ACPI and PCI compliant power manage-
ment function.
2.0 FEATURES
2.1 Industry standard
s IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
s Support for IEEE802.3x flow control
s IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
PQFP128 (14x20x2.7mm)
ORDERING NUMBER: STE10/100
s PCI bus interface Rev. 2.2 compliant
s ACPI and PCI power management standard
compliant
s Support PC99 wake on LAN
2.2 FIFO
s Provides independent transmission and
receiving FIFOs, each 2k bytes long
s Pre-fetches up to two transmit packets to
minimize inter frame gap (IFG) to 0.96us
s Retransmits collided packet without reload from
host memory within 64 bytes.
s Automatically retransmits FIFO under-run
packet with maximum drain threshold until 3rd
time retry failure without influencing the
registers and transmit threshold of next packet.
Figure 1. STE10/100Block Diagram
Flow
Control
DMA
Tx FiFo
Rx FiFo
Manchester
Encoder
10 TX
Filter
4B/5B
Scrambler
Auto
Negotiation
5B/4B ^Descrambler
100 clock
Recovery
Manchester
Decoder
Transmitter
25Mhz
TX Freq.
Synth.
125Mhz
20Mhz
BaseLine
Adaptive
+
Restore
Equalization
_
Link
Polarity
10 clock
Recovery
September 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
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