STE10 Datasheet, PDF (18/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
22~ 20
TS
Transmit State. Reports the current transmission state only, no
000
RO
interrupt will be generated.
000: stop
001: read descriptor
010: transmitting
011: FIFO fill, read the data from memory and put into FIFO
100: reserved
101: reserved
110: suspended, unavailable transmit descriptor or FIFO
overflow
111: write descriptor
19~17
RS
Receive State. Reports current receive state only, no interrupt
000
RO
will be generated.
000: stop
001: read descriptor
010: check this packet and pre-fetch next descriptor
011: wait for receiving data
100: suspended
101: write descriptor
110: flush the current FIFO
111: FIFO drain, move data from receiving FIFO into memory
16
NISS Normal Interrupt Status Summary. Set if any of the following
0
RO/LH*
bits of CSR5 are asserted:
TCI, transmit completed interrupt (bit 0)
TDU, transmit descriptor unavailable (bit 2)
RCI, receive completed interrupt (bit 6)
15
AISS Abnormal Interrupt Status Summary. Set if any of the following
0
RO/LH*
bits of CSR5 are asserted:
TPS, transmit process stopped (bit 1)
TJT, transmit jabber timer time-out (bit 3)
TUF, transmit under-flow (bit 5)
RDU, receive descriptor unavailable (bit 7)
RPS, receive process stopped (bit 8)
RWT, receive watchdog time-out (bit 9)
GPTT, general purpose timer time-out (bit 11)
FBE, fatal bus error (bit 13)
14
----
reserved
13
FBE Fatal Bus Error.
0
RO/LH*
1: on occurrence of parity error, master abort, or target abort
(see bits 25~23 of CSR5). The STE10/100 will disable all bus
access. A software reset is required to recover from a parity
error.
12
---
reserved
11
GPTT General Purpose Timer Timeout, based on CSR11 timer
register
0
RO/LH*
10
---
reserved
9
RWT Receive Watchdog Timeout, based on CSR15 watchdog timer
0
RO/LH*
register
8
RPS Receive Process Stopped, receive state = stop
0
RO/LH*
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