STE10 Datasheet, PDF (48/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
6.4 Receive scheme and Receive early interrupt scheme
The following figure shows the difference of timing without early interrupt and with early interrupt.
Figure 12. Receive data flow (without early interrupt and with early interrupt)
incoming packet
receive FIFO operation
FIFO-to-host memory operation
interrupt
driver read header
higher layer process
driver read the rest data
receive early interrupt
driver read header(early)
higher layer process(early)
driver read the rest data
time
: without early interrupt
Figure 13. Detailed Receive Early interrupt flow
finish time
finish time
: with early interrupt
FIFO-to-host memory
i
receive early
driver read
higher layer
driver read the rest
The size of 1^st
descriptor is
programmed as the
header size in
advance
1^st
descriptor
full
2^nd descriptor
issue 2^nd
interrupt at end
of packet
finish
time
i
48/66