STE10 Datasheet, PDF (54/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
6.6 LED Display Operation
The STE10/100 provides 2 LED display modes; the detailed descriptions of their operation are described in the
PIN Description section.
s First mode - 3 LED displays:
100Mbps (on) or 10Mbps (off)
Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitting collision-free)
FD (Remains on when in Full duplex mode) or Collision (Blinks at 20Hz when collidions detected)
s Second mode – 4 LED displays:
100 Link (On when 100M link ok)
10 Link (On when 10M link ok)
Activity (Blinks at 10Hz when receiving or transmitting)
FD (Remains on when in Full duplex mode) or Collision (Blinks at 20Hz when collisions detected)
6.7 Reset Operation
6.7.1 Reset whole chip
There are two ways to reset the STE10/100: Hardware reset via RST# pin (to ensure proper reset operation,
the RST# signal should be asserted at least 100ms); and software reset via SWR (bit 0 of CSR0) being set to
1 (the STE10/100 will reset all circuits, set registers to their default values, and will clear SWR.
6.7.2 Reset Transceiver only
When XRST (bit 15 of XR0) is set to 1, the transceiver will reset its circuits, will initialize its registers to their
default values, and clear XRST.
6.8 Wake on LAN Function
The STE10/100 can assert a signal to wake up the system when it has received a Magic Packet from the net-
work. The Wake on LAN operation is described as follow.
s The Magic Packet format:
Valid destination address that can pass the address filter of the STE10/100
The payload of frame must include at least 6 contiguous ‘FF’ followed immediately by 16 repetitions of
IEEE address.
The frame can contain multiple ‘six FF + sixteen IEEE address’ pattern.
Valid CRC
s The Wake on LAN operation
The Wake on LAN enable function is controlled by WOL (bit 18 of CSR18), which is loaded from
EEPROM after reset or programmed by driver software. If WOL is set and the STE10/100 receives a
Magic Packet, it will assert the PME# signal (active low) to indicate reception of a wake up frame and
will set the PME status bit (bit 15 of CSR20).
6.9 ACPI Power Management Function
The STE10/100 has a built-in capability for Power Management (PM) which is controlled by the host system
The STE10/100 will provide:
s Compatibility with Device Class Power Management Reference Specification
s Network Device Class, Draft proposal v0.9, October 1996
s Compatibility with ACPI, Rev 1.0, December 22, 1996
s Compatibility with PCI Bus Power Management Interface Specification, Rev 1.0, January 6, 1997
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