STE10 Datasheet, PDF (55/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
s Compatibility with AMD Magic Packet™ Technology.
6.9.1 Power States
s DO (Fully On)
In this state the STE10/100 operates with full functionality and consumes normal power. While in the
D0 state, if the PCI clock is lower than 16MHz, the STE10/100 may not receive or transmit frames
properly.
s D1, D2, and D3_hot
In these states, the STE10/100 doesn’t respond to any accesses except configuration space and full
function context in place. The only network operation the STE10/100 can initiate is a wake-up event.
s D3_cold (Power Removed)
In this state all function context is lost. When power is restored, a PCI reset must be asserted and the
function will return to D0.
s D3_hot (Software Visible D3)
When the STE10/100 is brought back to D0 from D3hot the software must perform a full initialization.
The STE10/100 in the D3hot state responds to configuration cycles as long as power and clock are
supplied. This requires the device to perform an internal reset and return to a power-up reset condition
without the RST# pin asserted.
Table 13. Power Stage
Device PCI Bus
State
State
Function
Context
D0
B0
Full function context in
place
Clock
Full speed
Power
Full
power
Supported
Actions to
Function
Any PCI
transaction
D1
D2
D3hot
D3cold
B0, B1
B0, B1,
B2
B0, B1,
B2
B3
Configuration
maintained. No Tx and
Rx except wake-up
events
Configuration
maintained. No Tx and
Rx
Configuration lost, full
initialization required
upon return to D0
All configuration lost.
Power-on defaults in
place on return to D0
Stopped to
Full speed
PCI configuration
access
Stopped to
Full speed
PCI configuration
access(B0, B1)
Stopped to
Full speed
PCI configuration
access(B0, B1)
No clock No power Power-on reset
Supported
Actions from
Function
Any PCI
transaction or
interrupt
Only wake-up
events
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