STE10 Datasheet, PDF (56/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
7.0 GENERAL EEPROM FORMAT DESCRIPTION
Table 14. Connection Type Definition
Offset
0
2
3
4
8
E
F
10
11
12
14
1F
20
22
24
26
28
29
2A
2E
30
7E
Length
2
1
1
4
6
1
1
1
1
2
0B
1
2
2
2
2
1
1
4
2
4E
2
Description
STE10/100 Signature: 0x81, 0x09
Format major version: 0x02,
old ROM format version 0x01 is for STE10/100-MAC only.
Format minor version: 0x00
Reserved
IEEE network address: ID1, ID2, ID3, ID4, ID5, ID6
IEEE ID checksum1:
Sm0=0, carry=0
SUM=Sm6 where Smi=(Smi-1<<1)+(carry from shift)+IDi
IEEE ID checksum2:
Reserved, should be zero.
PHY type, 0xFF: Internal PHY (STE10/100 only)
Reserved, should be zero.
Default Connection Type, see Table 15
Reserved, should be zero.
Flow Control Field,
00: Disable Flow Control function,
01: Enable Flow Control function
PCI Device ID.
PCI Vendor ID.
PCI Subsystem ID.
PCI Subsystem Vendor ID.
MIN_GNT value.
MAX_LAT value.
Cardbus CIS pointer.
CSR18 (CR) bit 31-16 recall data.
Reserved, should be zero.
CheckSum, the least significant two bytes of FCS for data stored in offset 0..7D of
EEPROM
56/66