STE10 Datasheet, PDF (33/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 8. Transceiver registers Descriptions
Bit #
Name
Descriptions
Default Val RW Type
0
EXT Extended register support.
Always 1, since STE10/100 supports extended register
1
RO
LL* = Latching Low and clear by read. LH* = Latching High and clear by read.
XR2(offset = bch) - PID1, PHY identifier 1
15~0
PHYID1 Part one of PHY Identifier.
0382h
RO
Assigned to the 3^rd to 18^th bits of the Organizationally Unique
Identifier.
XR3(offset = c0h) - PID2, PHY identifier 2
15~10
PHYID2 Part two of PHY Identifier.
010010b
RO
Assigned to the 19^th to 24^th bits of the Organizationally Unique
Identifier (OUI).
9~4
MODEL Model number of STE10/100.
6-bit manufacturer’s model number.
000001b
RO
3~0
REV Revision number of STE10/100.
4-bits manufacturer’s revision number.
0000b
RO
XR4(offset = c4h) - ANA, Auto-Negotiation Advertisement
15
NXTPG Next Page ability.
Always 0; STE10/100 does not provide next page ability.
0
RO
14
---
reserved
13
RF
Remote Fault function.
1: remote fault function present
0
R/W
12,11
---
reserved
10
FC
Flow Control function Ability.
1
R/W
1: supports PAUSE operation of flow control for full duplex link.
9
T4
100BASE-T4 Ability.
0
RO
Always 0; STE10/100 does not provide 100BASE-T4 ability.
8
TXF 100BASE-TX Full duplex Ability.
1: 100Base-TX full duplex ability supported
1
R/W
7
TXH 100BASE-TX Half duplex Ability.
1: 100Base-TX ability supported.
1
R/W
6
10F
10BASE-T Full duplex Ability.
1: 10Base-T full duplex ability supported.
1
R/W
5
10H 10BASE-T Half duplex Ability.
1: 10Base-T ability supported.
1
R/W
4~0
SF
Select field. Default 00001=IEEE 802.3
00001
RO
XR5(offset = c8h) - ANLP, Auto-Negotiation Link Partner ability
15
LPNP Link partner Next Page ability.
0: link partner without next page ability.
1: link partner with next page ability.
0
RO
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