STE10 Datasheet, PDF (24/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
CSR14(offset = 70h), WPDR –Wake-up Pattern Data Register
Offset
31
16 15
8
0000h
Wake-up pattern 1 mask bits 31:0
0004h
Wake-up pattern 1 mask bits 63:32
0008h
Wake-up pattern 1 mask bits 95:64
000ch
Wake-up pattern 1 mask bits 127:96
0010h
CRC16 of pattern 1
Reserved
7
0
Wake-up pattern 1 offset
0014h
0018h
001ch
0020h
0024h
Wake-up pattern 2 mask bits 31:0
Wake-up pattern 2 mask bits 63:32
Wake-up pattern 2 mask bits 95:64
Wake-up pattern 2 mask bits 127:96
CRC16 of pattern 2
Reserved
Wake-up pattern 2 offset
0028h
002ch
0030h
0034h
0038h
Wake-up pattern 3 mask bits 31:0
Wake-up pattern 3 mask bits 63:32
Wake-up pattern 3 mask bits 95:64
Wake-up pattern 3 mask bits 127:96
CRC16 of pattern 3
Reserved
Wake-up pattern 3 offset
003ch
0040h
0044h
0048h
004ch
Wake-up pattern 4 mask bits 31:0
Wake-up pattern 4 mask bits 63:32
Wake-up pattern 4 mask bits 95:64
Wake-up pattern 4 mask bits 127:96
CRC16 of pattern 4
Reserved
Wake-up pattern 4 offset
0050h
Wake-up pattern 5 mask bits 31:0
0054h
Wake-up pattern 5 mask bits 63:32
0058h
Wake-up pattern 5 mask bits 95:64
005ch
Wake-up pattern 5 mask bits 127:96
0060h
CRC16 of pattern 5
Reserved
Wake-up pattern 5 offset
1. Offset value is from 0-255 (8-bit width).
2. To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done.
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