STE10 Datasheet, PDF (46/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
6.3 Transmit Scheme and Transmit Early Interrupt
6.3.1 Transmit flow
Figure 9. The flow of packet transmit is shown as below.
Initialize descriptor
Place data in host memory
Set Own bit to 1
Write Tx demand poll command
Own = 0
Exit
STE10/100
checks descriptor
Own = 1
Transfer data to Tx FIFO
Deferring OR data less
than Tx threshold?
Back-off
Transmit data
across line
Collision
occurred?
Write descriptor
Generate interrupt
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