STE10 Datasheet, PDF (12/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val RW Type
0
IOSI Memory Space Indicator.
0
RO
1: means that the configuration registers map into I/O space.
CR11(offset = 2ch), SID - Subsystem ID.
31~16
SID
Subsystem ID. This value is loaded from EEPROM as a result
From
RO
of power-on or hardware reset.
EEPROM
15~ 0
SVID Subsystem Vendor ID. This value is loaded from EEPROM as
From
RO
a result power-on or hardware reset.
EEPROM
CR12(offset = 30h), BRBA - Boot ROM Base Address. This register should be initialized before accessing the
boot ROM space.
31~10
BRBA Boot ROM Base Address. This value indicates the address
X: b31~17
R/W
mapping of the boot ROM field as well as defining the boot
0: b16~10
RO
ROM size. The values of bit 16~10 are set to 0 indicating that
the STE10/100 supports up to 128kB of boot ROM.
9~1
---
reserved
RO R/W R/
W
0
BRE Boot ROM Enable. The STE10/100 will only enable its boot
0
R/W
ROM access if both the memory space access bit (bit 1 of
CR1) and this bit are set to 1.
1: enable Boot ROM. (if bit 1 of CR1 is also set)
CR13(offset = 34h), CP - Capabilities Pointer.
31~8
---
reserved
7~0
CP
Capabilities Pointer.
C0H
RO
CR15(offset = 3ch), CI - Configuration Interrupt
31~24
ML
Max_Lat register. This value indicates how often the STE10/
From
RO
100 needs to access to the PCI bus in units of 250ns. This
EEPROM
value is loaded from serial EEPROM as a result of power-on or
hardware reset.
23~16
MG
Min_Gnt register. This value indicates how long the STE10/
From
RO
100 needs to retain the PCI bus ownership whenever it
EEPROM
initiates a transaction, in units of 250ns. This value is loaded
from serial EEPROM as a result power-on or hardware reset.
15~ 8
IP
Interrupt Pin. This value indicates one of four interrupt request
01h
RO
pins to which the STE10/100 is connected.
01h: means the STE10/100 always connects to INTA#
7~0
IL
Interrupt Line. This value indicates the system interrupt
0
R/W
request lines to which the INTA# of STE10/100 is routed. The
BIOS will fill this field when it initializes and configures the
system. The STE10/100 driver can use this value to determine
priority and vector information.
CR16(offset = 40h), DS - Driver Space for special purpose.
31~16
---
reserved
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