STE10 Datasheet, PDF (16/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
CSR0(offset = 00h), PAR - PCI Access Register
31~25
---
reserved
24
MWIE Memory Write and Invalidate Enable.
0
1: enable STE10/100 to generate memory write invalidate
command. The STE10/100 will generate this command
while writing full cache lines.
0: disable generating memory write invalidate command. The
STE10/100 will use memory write commands instead.
R/W*
23
MRLE Memory Read Line Enable.
0
1: enable STE10/100 to generate memory read line command
when read access instruction reaches the cache line
boundary. If the read access instruction doesn’t reach the
cache line boundary then the STE10/100 uses the memory
read command instead.
R/W*
22
---
reserved
21
MRME Memory Read Multiple Enable.
0
1: enable STE10/100 to generate memory read multiple
commands when reading a full cache line. If the memory is
not cache-aligned, the STE10/100 uses the memory read
command instead.
R/W*
20~19
---
reserved
18,17
TAP Transmit auto-polling in transmit suspended state.
00: disable auto-polling (default)
01: polling own-bit every 200 us
10: polling own-bit every 800 us
11: polling own-bit every 1600 us
00
R/W*
16
---
reserved
15, 14
CAL Cache alignment. Address boundary for data burst, set after
00
reset
00: reserved (default)
01: 8 DW boundary alignment
10: 16 DW boundary alignment
11: 32 DW boundary alignment
R/W*
13 ~ 8
PBL Programmable Burst Length. This value defines the maximum 010000
number of DW to be transferred in one DMA transaction.
value: 0 (unlimited), 1, 2, 4, 8, 16(default), 32
R/W*
7
BLE Big or Little Endian selection.
0: little endian (e.g. INTEL)
1: big endian (only for data buffer)
0
R/W*
6~2
DSL
Descriptor Skip Length. Defines the gap between two
descriptors in the units of DW.
0
R/W*
1
BAR Bus arbitration
0: receive operations have higher priority
1: transmit operations have higher priority
0
R/W*
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