STE10 Datasheet, PDF (40/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 12. Transmit Descriptor Descriptions
Bit#
Name
Descriptions
13-12
----- Reserved
11
LO Loss of carrier
10
NC No carrier
9
LC Late collision
8
EC Excessive collision
7
HF Heartbeat fail
6-3
CC Collision count
2
----- Reserved
1
UF Under-run error
0
DE Deferred
TDES1
31
IC
Interrupt completed
30
LS Last descriptor
29
FS First descriptor
28,27
---
Reserved
26
AC Disable add CRC function
25
TER End of Ring
24
TCH 2nd address chain. Indicates that the buffer 2 address is the next descriptor address
23
DPD Disable padding function
22
---
Reserved
21-11
TBS2 Buffer 2 size
10-0
TBS1 Buffer 1 size
TDES2
31~0
BA1 Buffer Address 1. No alignment limitations imposed on the transmission buffer address.
TDES3
31~0
BA2 Buffer Address 2. No alignment limitations imposed on the transmission buffer address.
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