STE10 Datasheet, PDF (27/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
CSR18(offset = 88h), CR - Command Register, bit31 to bit16 automatically recall from EEPROM
31
D3CS D3cold power state wake up Support. If this bit is reset then
0
R/W
bit 31 of PMR0 will be reset to ‘0’. If this bit is asserted and an
from
auxiliary power source is detected then bit 31 of PMR0 will be EEPROM
set to ‘1’.
30-28
AUXCL Aux. Current Load. These three bits report the maximum
000b
R/W
3.3Vaux current requirements for STE10/100 chip. If bit 31 of
from
PMR0 is ‘1’, the default value is 111b, which means the
EEPROM
STE10/100 need 375 mA to support remote wake-up in
D3cold power state. Otherwise, the default value is 000b,
which means the STE10/100 does not support remote wake-
up from D3cold power state.
27-24
---
Reserved
23
4LEDmode This bit is used to control the LED mode selection.
_on
If this bit is reset, mode 1 (3 LEDs) is selected; the LEDs
definition is:
100/10 speed
Link/Activity
Full Duplex/Collision
If this bit is set, mode 2 (4 LEDs) is selected; the LEDs
definition is:
100 Link
10 Link
Activity
Full Duplex/Collision
0
R/W
from
EEPROM
22, 21
RFS
Receive FIFO size control
11: 1K bytes
10: 2K bytes
01,00: reserved
10
R/W
from
EEPROM
20
---
Reserved
19
PM
Power Management. Enables the STE10/100 Power
X
RO
Management abilities. When this bit is set into “0” the STE10/
from
100 will set the Cap_Ptr register to zero, indicating no PCI
EEPROM
compliant power management capabilities. The value of this
bit will be mapped to NC (CR1 bit 20). In PCI Power
Management mode, the Wake Up Frames include “Magic
Packet”, “Unicast”, and “Muliticast”.
18
WOL Wake on LAN mode enable. When this bit is set to ‘1’, then the
X
R/W
STE10/100 enters Wake On LAN mode and enters the sleep
from
state.
EEPROM
Once the STE10/100 enters the sleep state, it remains there
until: the Wake Up event occurs, the WOL bit is cleared, or a
reset (software or hardware) happens.
In Wake On LAN mode the Wake-Up frame is “Magic Packet”
only.
17~7
---
Reserved
6
RWP Reset Wake-up Pattern Data Register Pointer
0
R/W
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