STE10 Datasheet, PDF (23/66 Pages) STMicroelectronics – PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V

STE10/100
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val RW Type
30
CRCT CRC-16 Type
0: Initial contents = 0000h
1: Initial contents = FFFFh
0
R/W
29
WP1E Wake-up Pattern One Matched Enable.
0
R/W
28
WP2E Wake-up Pattern Two Matched Enable.
0
R/W
27
WP3E Wake-up Pattern Three Matched Enable.
0
R/W
26
WP4E Wake-up Pattern Four Matched Enable.
0
R/W
25
WP5E Wake-up Pattern Five Matched Enable.
0
R/W
24-18
---
Reserved
17
LinkOFF Link Off Detect Enable. The STE10/100 will set the LSC bit of
0
R/W
CSR13 after it has detected that link status has transitioned
from ON to OFF.
16
LinkON Link On Detect Enable. The STE10/100 will set the LSC bit of
0
R/W
CSR13 after it has detected that link status has transitioned
from OFF to ON.
15-11
---
Reserved
10
WFRE Wake-up Frame Received Enable. The STE10/100 will
0
R/W
include the “Wake-up Frame Received” event in its set of
wake-up events. If this bit is set, STE10/100 will assert
PMEST bit of PMR1 (CR49) after STE10/100 has received a
matched wake-up frame.
9
MPRE Magic Packet Received Enable. The STE10/100 will include Default 1 if
R/W
the “Magic Packet Received” event in its set of wake-up
PM & WOL
events. If this bit is set, STE10/100 will assert PMEST bit of bits of CSR
PMR1 (CR49) after STE10/100 has received a Magic packet. 18 are both
enabled.
8
LSCE Link Status Changed Enable. The STE10/100 will include the
0
R/W
“Link Status Changed” event in its set of wake-up events. If
this bit is set, STE10/100 will assert PMEST bit of PMR1 after
STE10/100 has detected a link status changed event.
7-3
---
Reserved
2
WFR Wake-up Frame Received,
X
R/W1C*
1: Indicates STE10/100 has received a wake-up frame. It is
cleared by writing a 1 or upon power-up reset. It is not
affected by a hardware or software reset.
1
MPR Magic Packet Received,
1: Indicates STE10/100 has received a magic packet. It is
cleared by writing a 1 or upon power-up reset. It is not
affected by a hardware or software reset.
X
R/W1C*
0
LSC Link Status Changed,
X
R/W1C*
1: Indicates STE10/100 has detected a link status change
event. It is cleared by writing a 1 or upon power-up reset. It
is not affected by a hardware or software reset.
R/W1C*, Read Only and Write one cleared.
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