LSM6DB0 Datasheet, PDF (25/66 Pages) STMicroelectronics – 3D accelerometer, 3D gyroscope and signal processor

LSM6DB0
Accelerometer and gyroscope functionality
7
Accelerometer and gyroscope functionality
7.1
Multiple reads (burst)
When only the accelerometer is activated and the gyroscope is in power down, starting from
OUT_X_XL (28h - 29h) multiple reads can be performed. Once OUT_Z_XL (2Ch - 2Dh) is
read, the system automatically restarts from OUT_X_XL (28h - 29h) (see Figure 7).
Figure 7. Multiple reads: accelerometer only
Read #1
Read #n
x,y,z
x,y,z
OUT_TEMP
(15-16)
OUT_X_XL OUT_Y_XL OUT_Z_XL
(28-29)
(2A-2B) (2C-2D)
OUT_X_XL OUT_Y_XL OUT_Z_XL
(28-29)
(2A-2B) (2C-2D)
When both accelerometer and gyroscope sensors are activated at the same ODR, starting
from OUT_X_G (18h - 19h) multiple reads can be performed. Once OUT_Z_XL (2Ch - 2Dh)
is read, the system automatically restarts from OUT_X_G (18h - 19h) (see Figure 8).
Figure 8. Multiple reads: accelerometer and gyroscope
Read #1
Read #n
x,y,z
x,y,z
OUT_TEMP _{OUT_X_G} OUT_Y_G _{OUT_Z_G OUT_X_XL OUT_Y_XL OUT_Z_XL}
(15-16)
(18-19) (1A-1B) (1C-1D) (28-29)
(2A-2B) (2C-2D)
OUT_X_G OUT_Y_G OUT_Z_G OUT_X_XL OUT_Y_XLOUT_Z_XL
(18-19) (1A-1B) (1C-1D) (28-29)
(2A-2B) (2C-2D)
7.2
FIFO
The LSM6DB0 embeds a 32 slots of 16-bit data FIFO for each of the gyroscope’s three
output channels, yaw, pitch and roll, and 16-bit data FIFO for each of the accelerometer’s
three output channels, X, Y and Z. This allows consistent power saving for the system, since
the host processor does not need to continuously poll data from the sensor, but it can wake
up only when needed and burst the significant data out from the FIFO. This buffer can work
accordingly to five different modes: Bypass mode, FIFO-mode, Continuous mode,
Continuous-to-FIFO mode and Bypass-to-Continuous. Each mode is selected by the
FMODE [2:0] bits in the FIFO_CTRL (2Eh) register. Programmable FIFO threshold status,
FIFO overrun events and the number of unread samples stored are available in the
FIFO_SRC (2Fh) register and can be set to generate dedicated interrupts on the INT1 pin
using the INT1_CTRL (0Ch) register.
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