LAN9117_08 Datasheet, PDF (98/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

5.4
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
MAC Control and Status Registers
Datasheet
These registers are located in the MAC module and are accessed indirectly through the MAC-CSR
synchronizer port. Table 5.6, "LAN9117 MAC CSR Register Map", shown below, lists the MAC registers
that are accessible through the indexing method using the MAC_CSR_CMD and MAC_CSR_DATA
registers (see sections MAC_CSR_CMD – MAC CSR Synchronizer Command Register and
MAC_CSR_DATA – MAC CSR Synchronizer Data Register).
INDEX
1
2
3
4
5
6
7
8
9
A
B
C
Table 5.6 LAN9117 MAC CSR Register Map
MAC CONTROL AND STATUS REGISTERS
SYMBOL
MAC_CR
ADDRH
ADDRL
HASHH
HASHL
MII_ACC
MII_DATA
FLOW
VLAN1
VLAN2
WUFF
WUCSR
REGISTER NAME
MAC Control Register
MAC Address High
MAC Address Low
Multicast Hash Table High
Multicast Hash Table Low
MII Access
MII Data
Flow Control
VLAN1 Tag
VLAN2 Tag
Wake-up Frame Filter
Wake-up Control and Status
DEFAULT
00040000h
0000FFFFh
FFFFFFFFh
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Revision 1.5 (07-11-08)
98
DATASHEET
SMSC LAN9117