LAN9117_08 Datasheet, PDF (92/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

5.3.20
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
Offset:
A4h
Size:
32 bits
This register is used to control the read and write operations with the MAC CSR’s
BITS DESCRIPTION
31
30
29-8
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
Reserved.
7-0 CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
TYPE
SC
R/W
RO
R/W
DEFAULT
0
0
-
00h
5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register
Offset:
A8h
Size:
32 bits
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write
operations with the MAC CSR’s
BITS DESCRIPTION
31-0 MAC CSR Data. Value read from or written to the MAC CSR’s.
TYPE
R/W
DEFAULT
00000000h
Revision 1.5 (07-11-08)
92
DATASHEET
SMSC LAN9117