LAN9117_08 Datasheet, PDF (12/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX
FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode
and will queue an entire frame before beginning transmission.
1.4
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a
conduit between the host interface and the MAC through which all transmitted and received data and
status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the
various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the
MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are
configurable in size, allowing increased flexibility.
1.5
Interrupt Controller
The LAN9117 supports a single programmable interrupt. The programmable nature of this interrupt
allows the user the ability to optimize performance dependent upon the application requirement. Both
the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing.
The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with
other devices. In addition, a programmable interrupt de-assertion interval is provided.
1.6
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the
LAN9117. It is accessible through the host bus interface via the CSRs. The GPIO signals can function
as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also
be configured to trigger interrupts with programmable polarity.
1.7
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9117. The serial EEPROM is optional and can be
programmed with the LAN9117 MAC address. The LAN9117 can optionally load the MAC address
automatically after power-on.
1.8
Power Management Controls
The LAN9117 supports comprehensive array of power management modes to allow use in power
sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported
by the LAN9117. An external PME (Power Management Event) interrupt is provided to indicate
detection of a wakeup event.
1.9
General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9117 and may be programmed to
issue a timed interrupt.
1.10 Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9117 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
Revision 1.5 (07-11-08)
12
DATASHEET
SMSC LAN9117