LAN9117_08 Datasheet, PDF (97/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
9
8
7-0
DESCRIPTION
EPC Time-out. If an EEPROM operation is performed, and there is no
response from the EEPROM within 30mS, the EEPROM controller will time-
out and return to its idle state. This bit is set when a time-out occurs
indicating that the last operation was unsuccessful.
Note:
If the EEDIO signal pin is externally pulled-high, EPC commands
will not time out if the EEPROM device is missing. In this case the
EPC Busy bit will be cleared as soon as the command sequence
is complete. It should also be noted that the ERASE, ERAL,
WRITE and WRAL commands are the only EPC commands that
will time-out if an EEPROM device is not present -and- the EEDIO
signal is pulled low
MAC Address Loaded. When set, this bit indicates that a valid EEPROM
was found, and that the MAC address programming has completed
normally. This bit is set after a successful load of the MAC address after
power-up, or after a RELOAD command has completed
EPC Address. The 8-bit value in this field is used by the EEPROM
Controller to address the specific memory location in the Serial EEPROM.
This is a Byte aligned address.
TYPE
R/WC
RO
R/W
DEFAULT
0
-
00h
5.3.24 E2P_DATA – EEPROM Data Register
Offset:
B4h
Size:
32 bits
This register is used in conjunction with the E2P_CMD register to perform read and write operations
with the Serial EEPROM
BITS DESCRIPTION
31-8 Reserved.
7:0 EEPROM Data. Value read from or written to the EEPROM.
TYPE
RO
R/W
DEFAULT
-
00h
SMSC LAN9117
97
DATASHEET
Revision 1.5 (07-11-08)