LAN9117_08 Datasheet, PDF (17/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.5 System and Power Signals
PIN
NO.
NAME
6
Crystal 1
SYMBOL
XTAL1
5
Crystal 2
95
Reset
XTAL2
nRESET
70
Wakeup Indicator
PME
71,73,
84,90,
91
Reserved
Reserved
BUFFER NUM
TYPE
PINS
lclk
1
Oclk
1
IS
1
(PU)
O8/OD8
1
5
DESCRIPTION
External 25MHz Crystal Input.
Can also be connected to single-
ended TTL oscillator. If this method is
implemented, XTAL2 should be left
unconnected.
External 25MHz Crystal output.
Active-low reset input. Resets all logic
and registers within the LAN9117
This signal is pulled high with a weak
internal pull-up resistor. If nRESET is
left unconnected, the LAN9117 will
rely on its internal power-on reset
circuitry
Note:
The LAN9117 must always
be read at least once after
power-up, reset, or upon
return from a power-saving
state or write operations will
not function. See Section
3.11, "Detailed Reset
Description," on page 42 for
additional information
When programmed to do so, is
asserted when the LAN9117 detects
a wake event and is requesting the
system to wake up from the
associated sleep state. The polarity
and buffer type of this signal is
programmable.
Note:
Detection of a Power
Management Event, and
assertion of the PME signal
will not wakeup the
LAN9117. The LAN9117 will
only wake up when it
detects a host write cycle
(assertion of nCS and
nWR). Although any write to
the LAN9117, regardless of
the data written, will wake-
up the device when it is in a
power-saving mode, it is
required that the
BYTE_TEST register be
used for this purpose.
No Connect
SMSC LAN9117
17
DATASHEET
Revision 1.5 (07-11-08)