LAN9117_08 Datasheet, PDF (121/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
A[7:1]
nCS, nRD
Data Bus
Figure 6.1 LAN9117 PIO Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.3 PIO Read Timing
SYMBOL DESCRIPTION
MIN
t_cycle
Read Cycle Time
45
t_csl
nCS, nRD Assertion Time
32
t_csh
nCS, nRD Deassertion Time
13
t_csdv
nCS, nRD Valid to Data Valid
t_asu
Address Setup to nCS, nRD Valid
0
t_ah
Address Hold Time
0
t_don
Data Buffer Turn On Time
0
t_doff
Data Buffer Turn Off Time
t_doh
Data Output Hold Time
0
TYP
MAX UNITS
ns
ns
ns
30
ns
ns
ns
ns
7
ns
ns
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
SMSC LAN9117
121
DATASHEET
Revision 1.5 (07-11-08)