LAN9117_08 Datasheet, PDF (87/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
BITS
5-4
3
2
1
0
DESCRIPTION
TYPE
WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up
event detection as follows
00b -- No wake-up event detected
01b -- Energy detected
10b -- Wake-up frame or magic packet detected
11b -- Indicates multiple events occurred
WUPS bits are cleared by writing a ‘1’ to the appropriate bit. The device must
return to the D0 state (READY bit set) before these bits can be cleared.
Note:
In order to clear this bit, it is required that all event sources be
cleared as well. The event sources are decribed in Figure 3.11 PME
and PME_INT Signal Generationon page 41.
PME indication (PME_IND). The PME signal can be configured as a pulsed
output or a static signal, which is asserted upon detection of a wake-up
event.
When set, the PME signal will pulse active for 50mS upon detection of a
wake-up event.
When clear, the PME signal is driven continously upon detection of a wake-
up event.
The PME signal can be deactivated by clearing the WUPS bits, or by
clearing the appropriate enable (refer to Section 3.10.2.3, "Power
Managment Event Indicators," on page 41).
PME Polarity (PME_POL). This bit controls the polarity of the PME signal.
When set, the PME output is an active high signal. When reset, it is active
low. When PME is configured as an open-drain output this field is ignored,
and the output is always active low.
PME Enable (PME_EN). When set, this bit enables the external PME signal.
This bit does not affect the PME interrupt (PME_INT).
Device Ready (READY). When set, this bit indicates that LAN9117 is ready
to be accessed. This register can be read when LAN9117 is in any power
management mode. Upon waking from any power management mode,
including power-up, the host processor can interrogate this field as an
indication when LAN9117 has stabilized and is fully alive. Reads and writes
of any other address are invalid until this bit is set.
Note: With the exception of HW_CFG and PMT_CTRL, read access to
any internal resources is forbidden while the READY bit is cleared.
R/WC
R/W
R/W
NASR
R/W
RO
DEFAULT
00
0b
0b
0b
-
SMSC LAN9117
87
DATASHEET
Revision 1.5 (07-11-08)