LAN9117_08 Datasheet, PDF (90/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

5.3.16
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
GPT_CNT-General Purpose Timer Current Count Register
Datasheet
Offset:
90h
Size:
This register reflects the current value of the GP Timer.
32 bits
BITS DESCRIPTION
31-16 Reserved
15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
TYPE
RO
RO
DEFAULT
-
FFFFh
5.3.17 WORD_SWAP—Word Swap Control
Offset:
98h
Size:
32 bits
This register controls how words from the host data bus are mapped to the CRSs and Data FIFOs
inside the LAN9117. The LAN9117 always sends data from the Transmit Data FIFO to the network so
that the low order word is sent first, and always receives data from the network to the Receive Data
FIFO so that the low order word is received first.
BITS DESCRIPTION
31:0 Word Swap. If this field is set to 00000000h, or anything except
FFFFFFFFh, the LAN9117 maps words with address bit A[1]=1 to the high
order words of the CSRs and Data FIFOs, and words with address bit
A[1]=0 to the low order words of the CSRs and Data FIFOs. If this field is
set to FFFFFFFFh, the LAN9117 maps words with address bit A[1]=1 to the
low order words of the CSRs and Data FIFOs, and words with address bit
A[1]=0 to the high order words of the CSRs and Data FIFOs.
TYPE
R/W
NASR
DEFAULT
00000000h
Revision 1.5 (07-11-08)
90
DATASHEET
SMSC LAN9117