LAN9117_08 Datasheet, PDF (20/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 2.6 MII Interface Signals
PIN
NO.
NAME
40
Transmit Clock:
SYMBOL
TX_CLK
BUFFER
TYPE
I (PD)
36, 37, Transmit Data [3:0]
38, 39
TXD[3:0]
O8 (PD)
21
Transmit Enable
TX_EN
O8 (PD)
26
Receive Clock
25
Receive Error
RX_CLK
RX_ER
I (PD)
I (PD)
33
Collision Detect:
COL/
I (PD)
24, 23, Receive Data[3:0]
22, 75
32
Carrier Sense
29
Receive Data
Valid:
RXD[3:0]
CRS
RX_DV
I (PD)
I (PD)
I (PD)
30 Management Data
MDIO
I/O8
IO/External PHY (EXT_PHY_DET) (PD)
Detect
NUM
PINS
1
4
1
1
1
1
1
1
1
1
DESCRIPTION
Transmit Clock: 25MHz in 100Base-
TX mode. 2.5MHz in 10Base-T
mode.
Transmit Data 3-0: Data bits that are
accepted by the PHY for
transmission.
When the internal PHY is selected,
these signals are driven low (0).
Transmit Enable: Indicates that valid
data is presented on the TXD[3:0]
signals, for transmission.
When the internal PHY is selected,
this signal is driven low (0).
Receive Clock: 25MHz in 100Base-
TX mode. 2.5MHz in 10Base-T
mode.
Receive Error: Asserted bt the PHY
to indicate that an error was detected
somewhere in the frame presently
being transferred from the PHY.
MII Collision Detect: Asserted by the
PHY to indicate detection of collision
condition.
Receive Data 3-0: Data bits that are
sent from the PHY to the Ethernet
MAC.
Carrier Sense: Indicates detection of
carrier.
Receive Data Valid: Indicates that
recovered and decoded data nibbles
are being presented by the PHY on
RXD[3:0].
Management Data IO: When
SMI_SEL = 1, this pin is the MII SMI
serial IO bus pin.
External PHY Detect: This pin also
functions as a strap input, which can
be used to indicate the presence of
an external PHY.
See Note 2.2.
Note:
See Section 5.3.9,
"HW_CFG—Hardware
Configuration Register" for
more information on
SMI_SEL and
EXT_PHY_DET
Revision 1.5 (07-11-08)
20
DATASHEET
SMSC LAN9117