LAN9117_08 Datasheet, PDF (122/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
6.3
PIO Burst Reads
In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can
be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high
between bursts for the period specified.
A[7:5]
A[4:1]
nCS, nRD
Data Bus
Figure 6.2 LAN9117 PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.4 PIO Burst Read Timing
SYMBOL DESCRIPTION
MIN
t_csh
nCS, nRD Deassertion Time
13
t_csdv
nCS, nRD Valid to Data Valid
t_acyc
Address Cycle Time
45
t_asu
Address Setup to nCS, nRD valid
0
t_adv
Address Stable to Data Valid
t_ah
Address Hold Time
0
t_don
Data Buffer Turn On Time
0
t_doff
Data Buffer Turn Off Time
t_doh
Data Output Hold Time
0
TYP
MAX UNITS
ns
30
ns
ns
40
ns
ns
7
ns
ns
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Revision 1.5 (07-11-08)
122
DATASHEET
SMSC LAN9117