LAN9117_08 Datasheet, PDF (81/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
5.3.9 HW_CFG—Hardware Configuration Register
Offset:
74h
Size:
32 bits
This register controls the hardware configuration of the LAN9117 Ethernet Controller.
Note: The transmitter and receiver must be stopped before writing to this register. Refer to Section
3.13.8, "Stopping and Starting the Transmitter," on page 56 and Section 3.14.4, "Stopping and
Starting the Receiver," on page 60 for details on stopping the transmitter and receiver.
BITS DESCRIPTION
31-21 Reserved
20 Must Be One (MBO). This bit must be set to “1” for normal device
operation.
16-19
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values
to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for
both TX data and TX commands.
The RX Status and data FIFOs consume the remaining space, which is
equal to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 82 for more information.
15-7 Reserved
6-5 PHY Clock Select (PHY_CLK_SEL). This field is used to switch between
the internal and external MII clocks (RX_CLK and TX_CLK). This field is
encoded as follows:
[6] [5]
MII Clock Source
---------------------------------------------------
00
Internal PHY
01
External MII Port
10
Clocks Disabled
11
Internal PHY
Notes:
„ This field does not control multiplexing of the SMI port or other MII signals.
„ There are restrictions on the use of this field. Please refer to Section 3.12,
"MII Interface - External MII Switching," on page 44 for details.
4 Serial Management Interface Select (SMI_SEL). This bit is used to switch
the SMI port (MDIO and MDC) between the internal PHY and the external
MII port. When this bit is cleared to ‘0’, the internal PHY is selected, and all
SMI transactions will be to the internal PHY. When this bit is set to ‘1’, the
external MII port is selected, and all SMI transactions will be to the external
PHY. This bit functions independent of EXT_PHY_EN. When this bit is set,
the internal MDIO and MDC signals are driven low. When this bit is cleared,
the external MIDIO signal is tri-stated, and the MDC signal is driven low.
Note: This bit does not control the multiplexing of other MII signals.
TYPE
RO
R/W
R/W
RO
R/W
R/W
DEFAULT
-
0
5h
-
00b
0
SMSC LAN9117
81
DATASHEET
Revision 1.5 (07-11-08)