LAN9117_08 Datasheet, PDF (124/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

6.5
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
RX Data FIFO Direct PIO Burst Reads
Datasheet
In this mode the upper address inputs are not decoded, and any burst read of the LAN9117 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9117. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines. In this mode, performance is improved by allowing an unlimited number of back-to-back
DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip
Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must
remain high for the period specified.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Note: The “Data Bus” width is 16 bits
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
SYMBOL
t_csh
t_csdv
t_acyc
t_asu
t_adv
t_ah
t_don
t_doff
t_doh
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
13
45
0
0
0
0
MAX
30
UNITS
ns
ns
ns
40
ns
ns
7
ns
ns
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Revision 1.5 (07-11-08)
124
DATASHEET
SMSC LAN9117