LAN9117_08 Datasheet, PDF(95/136 Page) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

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LAN9117_08 Datasheet, PDF (95/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

5.3.23 E2P_CMD â EEPROM Command Register

Offset:

B0h

Size:

32 bits

This register is used to control the read and write operations with the Serial EEPROM.

BITS DESCRIPTION

31 EPC Busy: When a 1 is written into this bit, the operation specified in the

EPC command field is performed at the specified EEPROM address. This

bit will remain set until the operation is complete. In the case of a read this

means that the host can read valid data from the E2P data register. The

E2P_CMD and E2P_DATA registers should not be modified until this bit is

cleared. In the case where a write is attempted and an EEPROM is not

present, the EPC Busy remains busy until the EPC Time-out occurs. At that

time the busy bit is cleared.

Note:

EPC busy will be high immediately following power-up or reset.

After the EEPROM controller has finished reading (or attempting to

read) the MAC address from the EEPROM the EPC Busy bit is

cleared.

TYPE

DEFAULT

SMSC LAN9117

DATASHEET

Revision 1.5 (07-11-08)

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