LAN9117_08 Datasheet, PDF (73/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Table 5.1 LAN9117 Direct Address Register Map (continued)
CONTROL AND STATUS REGISTERS
BASE ADDRESS
+ OFFSET
ACh
B0h
B4h
B8h - FCh
SYMBOL
AFC_CFG
E2P_CMD
E2P_DATA
RESERVED
REGISTER NAME
Automatic Flow Control Configuration
EEPROM command (The EEPROM is
indexed through this register)
EEPROM Data
Reserved for future use
DEFAULT
00000000h
00000000h
00000000h
-
5.3.1 ID_REV—Chip ID and Revision
Offset:
50h
Size:
32 bits
This register contains the ID and Revision fields for this design.
BITS DESCRIPTION
31-16 Chip ID. This read-only field identifies this design
15-0 Chip Revision. This is the current revision of the chip.
TYPE
RO
RO
DEFAULT
0117h
0001h
SMSC LAN9117
73
DATASHEET
Revision 1.5 (07-11-08)