LAN9117_08 Datasheet, PDF (38/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
EECS
EECLK
EEDIO (OUTPUT)
EEDIO (INPUT)
1
0
0
0
1
t_CSL
D7
D0
Figure 3.10 EEPROM WRAL Cycle
Table 3.8, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for
each EEPROM operation.
Table 3.8 Required EECLK Cycles
OPERATION
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
REQUIRED EECLK CYCLES
10
10
10
10
18
18
18
3.9.2.2
3.9.2.3
3.9.2.4
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 95 and Section 5.3.24,
"E2P_DATA – EEPROM Data Register," on page 97 for a detailed description of these registers.
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to Section 6.9, "EEPROM Timing," on page 128 for detailed EEPROM timing specifications.
Revision 1.5 (07-11-08)
38
DATASHEET
SMSC LAN9117