LAN9117_08 Datasheet, PDF (89/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Bits
4:3
2:0
Description
GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
GPO3 – bit 3
GPO4 – bit 4
GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is
reflected on GPIOn. When read, GPIOn reflects the current state of the
corresponding GPIO pin.
GPIO0 – bit 0
GPIO1 – bit 1
GPIO2 – bit 2
Type
R/W
R/W
Default
00
000
[22]
[21]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Table 5.4 EEPROM Enable Bit Definitions
[20]
EEDIO FUNCTION
EECLK FUNCTION
0
EEDIO
EECLK
1
GPO3
GPO4
0
Reserved
1
GPO3
RX_DV
0
Reserved
1
TX_EN
GPO4
0
TX_EN
RX_DV
1
TX_CLK
RX_CLK
5.3.15 GPT_CFG-General Purpose Timer Configuration Register
Offset:
8Ch
Size:
32 bits
This register configures the General Purpose timer. The GP Timer can be configured to generate host
interrupts at intervals defined in this register.
BITS DESCRIPTION
31-30 Reserved
TYPE
RO
29 GP Timer Enable (TIMER_EN). When a one is written to this bit the GP
R/W
Timer is put into the run state. When cleared, the GP Timer is halted. On
the 1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh.
28-16 Reserved
RO
15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded R/W
into the GP-Timer.
DEFAULT
-
0
-
FFFFh
SMSC LAN9117
89
DATASHEET
Revision 1.5 (07-11-08)