LAN9117_08 Datasheet, PDF(83/136 Page) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

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LAN9117_08 Datasheet, PDF (83/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

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High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

Datasheet

RX FIFO Size = 16384 â 6144 = 10240 Bytes (10KB)

RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)

RX Data FIFO Size = 10240 â 640 = 9600 Bytes

Table 5.3 shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table

are reserved and should not be used.

Note: The RX data FIFO is considered full 4 DWORDs before the length that is specified in the

HW_CFG register.

TX_FIF_SZ

Table 5.3 Valid TX/RX FIFO Allocations

TX DATA FIFO

SIZE (BYTES)

1536

2560

3584

4608

5632

6656

7680

8704

9728

10752

11776

12800

13824

TX STATUS FIFO

SIZE (BYTES)

512

RX DATA FIFO

SIZE (BYTES)

13440

12480

11520

10560

9600

8640

7680

6720

5760

4800

3840

2880

1920

RX STATUS FIFO

SIZE (BYTES)

896

832

768

704

640

576

512

448

384

320

256

192

128

In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K

bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by

the host.

As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO.

Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames.

This is in addition to any TX data that may be queued in the TX data FIFO.

Conversely, as data is received by the LAN9117, it is moved from the MAC to the RX MIL FIFO, and

then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX

MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is

made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter

(RX_DROP) is incremented.

RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate

independent of the TX adatand RX data and status FIFOs. FIFO levels set for the RX and TX data

and Status FIFOs do not take into consideration the MIL FIFOs.

SMSC LAN9117

DATASHEET

Revision 1.5 (07-11-08)

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