LAN9117_08 Datasheet, PDF (34/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
EEPROM Write
Idle
EEPROM Read
Idle
Write Data
Regis ter
W r ite
Command
Regis ter
Busy Bit = 0
Read
Command
Regis ter
Write
Command
Re gis te r
Read
Command
Re gis te r
Busy Bit = 0
Read Data
Re gis te r
3.9.2.1
Figure 3.3 EEPROM Access Flow Diagram
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
page 95 for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
Revision 1.5 (07-11-08)
34
DATASHEET
SMSC LAN9117