LAN9117_08 Datasheet, PDF (78/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

5.3.5
High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
BYTE_TEST—Byte Order Test Register
Datasheet
Offset:
64h
Size:
32 bits
This register can be used to determine the byte ordering of the current configuration
BITS DESCRIPTION
31:0 Byte Test
TYPE
RO
DEFAULT
87654321h
5.3.6 FIFO_INT—FIFO Level Interrupts
Offset:
68h
Size:
32 bits
This register configures the limits where the FIFO Controllers will generate system interrupts.
BITS DESCRIPTION
31-24
TX Data Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
23-16
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
15-8 Reserved
7-0 RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
TYPE
R/W
R/W
RO
R/W
DEFAULT
48h
00h
-
00h
Revision 1.5 (07-11-08)
78
DATASHEET
SMSC LAN9117