LAN9117_08 Datasheet, PDF (59/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Host Read
Order
1st
2nd
Last
31
0
Optional offset DWORD0
.
.
Optional offset DWORDn
ofs + First Data DWORD
.
.
.
.
Last Data DWORD
Optional Pad DWORD0
.
.
Optional Pad DWORDn
Figure 3.19 RX Packet Format
3.14.3
Note 3.17 The LAN9117 host bus interface supports 16-bit bus transfers; internally, all data paths are
32-bits wide. Figure 3.19 describes the host read ordering for pairs of atomic 16-bit
transactions.
RX Status Format
BITS
31
30
29:16
15
14
13
12
DESCRIPTION
Reserved. This bit is reserved. Reads 0.
Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing
filtering.
Packet Length. The size, in bytes, of the corresponding received frame.
Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the
Internal logical “or” of bits 11,7,6 and 1.
Reserved. These bits are reserved. Reads 0.
Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address.
Length Error (LE). When set, this bit indicates that the actual length does not match with the
length/type field of the received frame.
SMSC LAN9117
59
DATASHEET
Revision 1.5 (07-11-08)