LAN9117_08 Datasheet, PDF (18/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Table 2.5 System and Power Signals (continued)
Datasheet
PIN
NO.
74
NAME
SYMBOL
10/100 Selector
SPEED_SEL
BUFFER NUM
TYPE
PINS
I (PU)
1
100, General Purpose
GPIO[2:0]/
IS/O12/
3
99, 98
I/O data,
LED[3:1]
OD12
nLED1 (Speed
Indicator),
nLED2 (Link &
Activity Indicator),
nLED3 (Full-
Duplex
Indicator).
10
RBIAS
9
Test Pin
2
20,28,
35,
42,48,
55,61,
97
Internal Regulator
Power
+3.3V I/O Power
RBIAS
ATEST
VREG
VDD_IO
AI
1
I
1
P
1
P
8
DESCRIPTION
This signal functions as a
configuration input on power-up and
is used to select the default Ethernet
settings. Upon deassertion of reset,
the value of the input is latched. This
signal functions as shown in
Table 2.2, "Default Ethernet Settings",
below.
General Purpose I/O data: These
three general-purpose signals are
fully programmable as either push-
pull output, open-drain output or input
by writing the GPIO_CFG
configuration register in the CSR’s.
They are also multiplexed as GP LED
connections.
GPIO signals are Schmitt-triggered
inputs. When configured as LED
outputs these signals are open-drain.
nLED1 (Speed Indicator). This
signal is driven low when the
operating speed is 100Mbs, during
auto-negotiation and when the cable
is disconnected. This signal is driven
high only during 10Mbs operation.
nLED2 (Link & Activity Indicator).
This signal is driven low (LED on)
when the LAN9117 detects a valid
link. This signal is pulsed high (LED
off) for 80mS whenever transmit or
receive activity is detected. This
signal is then driven low again for a
minimum of 80mS, after which time it
will repeat the process if TX or RX
activity is detected. Effectively, LED2
is activated solid for a link. When
transmit or receive activity is sensed
LED2 will flash as an activity
indicator.
nLED3 (Full-Duplex Indicator). This
signal is driven low when the link is
operating in full-duplex mode.
PLL Bias: Connect to an external
12.0K ohm 1.0% resistor to ground.
Used for the PLL Bias circuit.
This pin must be connected to VDD
for normal operation.
3.3V input for internal voltage
regulator
+3.3V I/O logic power supply pins
Revision 1.5 (07-11-08)
18
DATASHEET
SMSC LAN9117