LAN9117_08 Datasheet, PDF (61/136 Pages) SMSC Corporation – High Performance Single-Chip 10/100 Non-PCI Ethernet Controller

High Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Chapter 4 Internal Ethernet PHY
4.1
Top Level Functional Description
Functionally, the internal PHY can be divided into the following sections:
„ 100Base-TX transmit and receive
„ 10Base-T transmit and receive
„ Internal MII interface to the Ethernet Media Access Controller
„ Auto-negotiation to automatically determine the best speed and duplex possible
„ Management Control to read status registers and write control registers
MAC
TX_CLK
100M
PLL
Internal
MII 25 MHz by 4 bits
MII
25MHz 4B/5B 25MHz by Scrambler
by 4 bits _Encoder 5 bits _{and PISO}
NRZI
Converter
NRZI
125 Mbps Serial
MLT-3
Tx
Converter ^MLT-3 Driver
MLT-3
MLT-3 Magnetics
RJ45
MLT-3
CAT-5
Figure 4.1 100Base-TX Data Path
4.2
4.2.1
100Base-TX Transmit
The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 4.1. Each 4-bit data-nibble
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles,
0 through F. The remaining code-groups are given letter designations with slashes on either side. For
example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc.
The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is
bypassed the 5^th transmit data bit is equivalent to TX_ER.
SMSC LAN9117
61
DATASHEET
Revision 1.5 (07-11-08)