SAB80515 Datasheet, PDF (96/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

On-Chip Peripheral Components
The second configuration which should be noted is when compare function is combined with
negative transition activated interrupts. lf the port latch of port P1.0 contains a 1, the interrupt
request flags IEX2 will immediately be set after enabling the compare mode for the CRC register.
The reason is that first the external interrupt input is controlled by the pin’s level. When the compare
option is enabled the interrupt logic input is switched to the internal compare signal, which carries
a low level when no true comparison is detected. So the interrupt logic sees a 1-to-0 edge and sets
the interrupt request flag.
An unintentional generation of an interrupt during compare initialization can be prevented if the
request flag is cleared by software after the compare is activated and before the external interrupt
is enabled.
7.5.3 Capture Function
Each of the three compare/capture registers CC1 to CC3 and the CRC register can be used to latch
the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for
this function. In mode 0, an external event latches the timer 2 contents to a dedicated capture
register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit
capture register. This mode is provided to allow the software to read the timer 2 contents "on-the-
fly".
In mode 0, the external event causing a capture is
– for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1
– for the CRC register: a positive or negative transition at the corresponding pin, depending
on the status of the bit I3FR in SFR T2CON. lf the edge flag is
cleared, a capture occurs in response to a negative transition; if the
edge flag is set a capture occurs in response to a positive transition
at pin P1.0/INT3/ CC0.
In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to
contain a one (1). The external input is sampled in every machine cycle. When the sampled input
shows a low (high) level in one cycle and a high (low) in the next cycle, a transition is recognized.
The timer 2 contents is latched to the appropriate capture register in the cycle following the one in
which the transition was identified.
In mode 0 a transition at the external capture inputs of registers CC0 to CC3 will also set the
corresponding external interrupt request flags IEX3 to IEX6. lf the interrupts are enabled, an
external capture signal will cause the CPU to vector to the appropriate interrupt service routine.
In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture
register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The value
written to the dedicated capture register is irrelevant for this function. The timer 2 contents will be
latched into the appropriate capture register in the cycle following the write instruction. In this mode
no interrupt request will be generated.
Semiconductor Group
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