SAB80515 Datasheet, PDF (28/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

External Bus Interface
Timing
The timing of the external bus interface, in particular the relationship between the control signals
ALE, PSEN, RD and information on port 0 and port 2, is illustrated in figure 5-1 a) and b).
Data memory:
in a write cycle, the data byte to be written appears on port 0 just before WR is
activated, and remains there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at port 0 before the read strobe is deactivated.
Program memory: signal PSEN functions as a read strobe. For further information see section 5.2.
External Program Memory Access
The external program memory is accessed under two conditions:
– whenever signal EA is active; or
– whenever the program counter (PC) contains a number that is larger than 01FFFH.
This requires the ROM-less versions SAB 80C535/80535 to have EA wired low to allow the lower
8 K program bytes to be fetched from external memory.
When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an
output function and may not be used for general-purpose I/O. The contents of the port 2 SFR
however is not affected. During external program memory fetches port 2 lines output the high byte
of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR
(depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).
Since the SAB 80C535/80535 has no internal program memory, accesses to program memory are
always external, and port 2 is at all times dedicated to output the high-order address byte. This
means that port 0 and port 2 of the SAB 80C535/80535 can never be used as general-purpose I/O.
This also applies to the SAB 80C515/80515 when it is operated with only an external program
memory.
Semiconductor Group
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