SAB80515 Datasheet, PDF (40/270 Pages) Siemens Semiconductor Group – 8-Bit Single-Chip Microcontroller Family

On-Chip Peripheral Components
If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will
switch to IH state.
If the latch is loaded with "0", the pin will be in OL state.
If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then
switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur.
At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin
is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will
remain in this state or will switch to IH (=SOH) state.
If it is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s trip point
after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds
the drive capability of p2 (I_IL), the pin might remain in the IL state and provide a week "1" until the
first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of
the external circuitry.
The same is true if a pin is used as bidirectional line and the external circuitry is switched from
outpout to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities.
If the load exceeds I_IL the pin can be forced to "1" by writing a "0" followed by a "1" to the port pin.
Port 0, in contrast to ports 1 through 5, is considered as "true" bidirectional, because the port 0 pins
float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET
in the P0 output driver (see figure 7-4 a) ) is used only when the port is emitting 1 s during the
external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are
used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs
off and the pin floats. In that condition it can be used as high-impedance input. lf port 0 is configured
as general I/O port and has to emit logic high level (1), external pullups are required.
Figure 7-4 a)
Port 0 Circuitry
Semiconductor Group
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